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ACE's open compiler development system CoSy
is widely recognized for its cost-effective, automated
generation of high-quality, high-performance compilers
for a broad range of processor architectures, including
DSP, SIMD, VLIW, multi-threading and heterogeneous multicore
processor systems.
With the seamless integration of CoWare's Processor
Designer and ACE's CoSy technology, users can both generate
C compilers during architecture creation and exploit
CoSy features to produce best in class compilers as an
integral part of the design flow.
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ARC International is a provider
of uniquely optimized SoC solutions for exceptionally competitive
markets.
ARC VTOC products use the technology behind the ARC xCAM modeller to automatically
provide 100% cycle accurate C++ and SystemC models of customers' ARC and/or
non-ARC IP written in Verilog or VHDL. Since the models are pure software and
can be compiled to binary, they also are ideal for secure shipment of IP models
to third parties.
ARC VTOC SystemC models are automatically plug-n-play with the CoWare tools.
All the debug features of SCML can be applied to VTOC models to ensure visibility
of the underlying RTL hierarchy.
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Carbon Design Systems model
generation technology automatically creates high speed software models directly from RTL. These reusable models link
directly into CoWare Platform Architect for deployment throughout
the enterprise. Carbon's Replay and OnDemand technologies
accelerate software debug times and speed execution of
the complete system platform. Together, the joint
flow enables designers to perform the detailed analysis
necessary to understand how a system's software and hardware
really interact.
CoWare & Carbon
Webinar
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Testimonial
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CriticalBlue's Cascade solution synthesizes
reprogrammable, application-optimized coprocessors which
accelerate unmodified host processor software while reducing
power consumption. In addition to synthesizable RTL and
executable microcode, Cascade generates a SystemC representation
of the coprocessor which can be used for full system verification
in CoWare's Platform Architect in combination with CoWare's
transaction level AMBA bus simulator.
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Esterel Studio delivers the full expected benefits
of ESL synthesis, providing an automated path from ESL to
RTL by generating consistent VHDL/Verilog and SystemC implementations
from a single and formally verified Esterel Studio IP executable
specification.
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EVE offers the broadest
hardware-assisted verification solutions of the market,
from acceleration, to fast emulation, to friendly prototyping
with the most cycles per dollar. EVE's ZeBu (Zero
Bugs) verification platforms handle hardware debug, regression
testing, HW/SW integration, and SW development. When linked
with CoWare Platform Architect designers can leverage the
system modeling environment with emulated hardware. EVE
products lead to a significant shortening of the overall
verification cycle of complex integrated circuits and electronic
systems design.
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Forte's innovative SystemC behavioral synthesis technology
allows design teams creating complex electronic systems from algorithmic
designs using ASICs, FPGAs, and SoCs to significantly reduce their overall
design and verification time. Users of CoWare Platform Architect can integrate
subsystem RTL generated using Forte Cynthesizer behavioral synthesis to validate
candidate RTL implementations in the system with embedded software.
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Javelin Design Automation specializes in System Physical Prototyping
(SPP) for Systems-in-Silicon. Javelin's platform enables concurrent design,
bridging ESL and RTL to implementation.
Javelin's integration with CoWare Platform Architect provides system designers
with fast, timely and quality feedback on physical feasibility as they explore
multiple possible architectures and design structures.
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JEDA is focused on developing verification
automation tools for SystemC to improve quality and reduce
the verification effort. JEDA's advanced verification capabilities
for CoWare Platform Architect and Model Designer enable runtime
performance and functional checking. It also enables you
to measure your test bench quality through data coverage
results.
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Synfora has developed the PICO platform - a system of tools
and IP that creates complex application engines from sequential, untimed
C algorithms.
An application engine is an integrated hardware/software sub-system for audio,
video, imaging and wireless applications (codec, modem) that rapidly and consistently
integrate into a platform SoC. PICO enables design teams to predictably deliver
complex consumer SoC's by partitioning the design into manageable sub-systems.
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