CoWare Demo & Download Center

Demos

CoWare Platform Architect and CoWare Virtual Platforms

CoWare's Platform Architecture Design Solution focuses on the challenges associated with the optimization and performance validation of the backbone interconnect and global memory subsystem of the SoC. Architects are looking to ESL methods to greatly improve the analysis and decision making process. Software developers and integration and test teams are asked to deliver better products faster and with higher quality. IP, semiconductor and electronics companies are using CoWare Virtual Platforms to address the challenges associated with low-level and hardware-dependent software development, application software development, and to perform system integration and test. CoWare virtual hardware platforms are fast and scalable simulations of the system hardware, including the device hardware and the environment it evolves in. Sign in here if you have already registered.

Programmable Accelerator Design using CoWare® Processor Designer

Today's designs require support for multiple standards such as H.264, VC-1 and LTE. This results in the need for more flexibility. This demonstration will show how you can use CoWare Processor Designer to develop programmable accelerators for next-generation video, wireless or security products. With this breakthrough technology, you can apply your application and hardware design knowledge to achieve processing performance way beyond any off-the-shelf CPU or DSP with the amount of programmability required by your application. We will also demonstrate how to apply the latest enhancements of CoWare Processor Designer to reduce power consumption. Sign in here if you have already registered.

	Introduction to CoWare Platform Architect This 3 minute demo introduction shows how CoWare Platform Architect can help you develop and use SystemC transaction-level virtual hardware platforms for Platform Architecture Design and Platform Verification.
	Assembling Virtual Hardware Platforms with CoWare Platform Architect This 5 minute demo shows how CoWare Platform Architect can help you assemble SystemC transaction-level IP models to create a virtual hardware platform for Platform Architecture Design, Software Development, and Platform Verification.
	Virtual Hardware Platform Debug and Analysis with CoWare Platform Architect This 5 minute demo shows how CoWare Platform Architect can help you perform platform-level debug and analysis on a SystemC transaction-level virtual hardware platform for Platform Architecture Design and Platform Verification.
	SystemC Component Development and Unit Test with CoWare Platform Architect This 5 minute demo shows how CoWare Platform Architect can help you create and test highly reusable, user-defined SystemC transaction-level peripheral components for integration in a SystemC transaction-level virtual hardware platform.
	Creating Programmable Accelerators with CoWare Processor Designer In this demonstration you will experience how CoWare Processor Designer's automated, application-specific embedded processor design and optimization environment can slash months from processor hardware design time and engineer-months from the creation of application processor-specific software development tools.
	Creation, Packaging for Distribution and Use of CoWare Virtual Platforms for Software Development In this demonstration you will experience the power of CoWare Virtual Platform as a better alternative to hardware.
	DSP Algorithm Design Using CoWare Signal Processing Designer This demo highlights CoWare's solution for mastering the development of complex DSP system specifications and verification of implemented DSP components. Modeling, simulation, debug and analysis across different modeling paradigms for algorithms, analog and digitial circuits are demonstrated.

Downloads

Transaction-level Modeling and SCML Source-code Kit
CoWare has developed a source code implementation of the SCML API library which is available today. The purpose is to protect user investment in user-defined SCML peripheral models by enabling their use in other IEEE 1666 compatible SystemC simulation environments.