ESL 2.0 refers to a second generation of ESL solutions that enable the design and development of processor-centric, software-intensive products with complex interconnect and memory architectures in a production environment.

During the Design Automation Conference, you’ll have the opportunity to learn more by attending our ESL 2.0 Solution Sessions. If you are new to the world of electronic system-level (ESL) design and want to learn more, register for our Corporate Overview session.

CoWare ESL 2.0 Solution Sessions -- register today.

CoWare Corporate Overview
Monday, June 9 at 1:00 pm & 4:00 pm
Tuesday, June 10 at 1:00 pm & 5:00 pm
Wednesday, June 11 at 9:00 am & 4:00 pm

This session will be lead by CoWare executives where you have the opportunity to learn more about CoWare’s key markets, our strategy, solutions, partners and customer successes. This session is intended for managers and decision makers who are new to Electronic System-Level Design and want to learn more about this exciting market and how companies are benefitting from working with CoWare, the ESL design leader.

Beyond the Spreadsheet: Traffic Generation and ESL Performance Analysis for Platform Architecture Design
Monday, June 9 at 11:00 am
Tuesday, June 10 at 3:00 pm
Wednesday, June 11 at 10:00 am

Are worst-case estimates giving you the spreadsheet blues? Are you struggling to predict the actual system performance of your next SoC—or even an average?  

Today's multi-mode, multi-application systems place a demanding set of performance requirements on the global resources of the SoC. Using spreadsheets to estimate bandwidth is no longer viable, when dynamic workloads make it impossible to predict performance across each and every possible configuration of the interconnect and memory subsystem. Real simulation and architecture performance measurement is needed—before software is available—to optimize results and avoid over-design.

Using a multimedia phone platform example, we will show how critical elements of a platform—application traffic, interconnect, and memory—are quickly modeled to enable architecture exploration in CoWare Platform Architect. You will learn how to assemble a platform and generate transaction traffic, using models available in the CoWare Model Library along with your existing RTL, to explore its performance with accurate and measurable results. In addition, we will highlight how the same performance model can be reused to analyze and solve run-time performance issues found during development of the embedded software.

Learn how CoWare ESL 2.0 Solutions help you to lower your product development cost, validate architecture performance to avoid overdesign, and speed system integration.

Audience: System Architects, Hardware Designers, and Verification Engineers

Developing Programmable Hardware Accelerators in Less than Four Months
Monday, June 9 at 10:00 am
Tuesday, June 10 at 4:00 pm
Wednesday, June 11 at 11:00 am

Are you designing HW accelerators for video, image processing, security, multimedia or wireless applications and you need more flexibility? Is your next project targeting new standards like H.264, VC-1 or next wireless standard like LTE? If you answered “yes” to any of these questions, you won’t want to miss this session at DAC!

During this session, we will show how current CoWare customers have used CoWare Processor Designer to develop programmable accelerators for their next-generation video, wireless or security products. With this breakthrough technology, you can apply your application and hardware design knowledge to achieve processing performance way beyond any off-the-shelf CPU or DSP with the amount of programmability required by your application. We will demonstrate how to apply the latest enhancements to CoWare Processor Designer, to reduce power consumption. We will also present how the user can configure the interface specification for RTL code generation to connect to any existing memory subsystem or interconnect in RTL without manual modifications of the code. The unified and very comprehensive debugging solution for the ISS, the RTL as well as the final silicon in a board completes the design flow presentation.

Target Audience: System architects and hardware designers.

Get Ready for Next-Generation Wireless System Design—LTE Is Here
Monday, June 9 at 3:00 pm
Wednesday, June 11 at 5:00 pm

Are you implementing WiMAX or LTE…or both? Are you still trying to track the moving parts of the standard, while optimizing your algorithms? Are you concerned about your protocol software working with your physical layer hardware?

If you think the answer to all of these questions is to patch C-code with MATLAB interfaces, then you are losing too much time. If you think there is enough room in your fixed-point specification for implementation loss, then you have overdesigned. If you believe that DSP algorithms and protocols are being developed in two different teams, you are missing out while your competitor is organizing for success. Learn how CoWare ESL 2.0 Solutions help you lower your algorithm modeling cost, avoid overdesign of high performance DSP functions and speed up system integration. Experience high speed, high capacity simulation integrated into ESL 2.0.

Target Audience: MATLAB users, algorithm designers, wireless system engineers, wireless IP providers, fabless and integrated semiconductor companies, system houses and Mil/Aero contractors.

Developing Software in a Virtual Environment: Bring It On
Tuesday, June 10 at 10:00 am
Wednesday, June 11 at 3:00 pm

Is your hardware not available soon enough? Are test benches too complex to set up or access? Are you missing the right tool to debug and analyze software? Do you want to provide something to your customers earlier? If you answered “yes” to any of these questions, you are ready to use virtual platforms for the development, integration and test of software.

You can now simulate at speeds close to and even faster than real-time, be in total control of your hardware and distribute it to your customers and partners. And, you can do all this right from your laptop! During this session, you will see first hand how a shared memory problem can be identified and debugged in ways not possible before. If you are developing a system-on-chip, a mobile phone, a consumer device, networking equipment or an automotive control unit, attend this session at DAC and experience how virtual platforms provide the tools that will set you free from the limitations of physical hardware.

Target Audience: software developers, software tools developers, hardware developers targeting solutions for software development, marketing and business development, IP, semiconductor, device
manufacturers and independent software vendor companies.

Using the New SystemC TLM-2.0 Standard for the Creation of Virtual Platforms for Software Development and Architecture Design
Wednesday, June 11 at 2:00 pm

During this session, we will provide a technical overview of the key elements in TLM-2.0 and illustrate the effective creation of standards-compliant TLM-2.0 models that satisfy the simulation speed and timing accuracy requirements of different ESL design tasks including software development, hardware and software performance analysis, and architecture design.

Target Audience: System architects and hardware designers

Partner Seminar: Automatic Model Creation for CoWare Platform Architect
Tuesday, June 10 at 10:00 am

Join CoWare and Carbon Design Systems as they demonstrate their solution for automatically generating models for use in CoWare’s Platform Architect and Signal Processing Designer environments.  These high-speed models are generated directly from RTL and enable design teams to perform earlier, more accurate architectural exploration and develop firmware in a completely virtual environment. The Carbon Model Studio product will be demonstrated to show the model creation flow. The created model will then be shown in a CoWare platform which will demonstrate its advanced profiling and hardware/software debug features.

All those in attendance will have a chance to win an Apple iPod Touch.

Panels

ESL Signoff: Fact or EDA Fiction?
Tuesday, June 10, 4:30 – 6:00, Rm. 210CD
Moderator: Gary Smith
CoWare Panelist: Dr. Tim Kogel

Multicore SoC Design is the Challenge! What’s the Solution?
Tuesday, June 10, 3:00 – 4:00, Rm. 207ABC
Moderator: Prof. Wolf
CoWare Panelist: Achim Nohl

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