Unable to attend the hands-on workshop on December
1st? Please register to attend:
One-hour Webinar:
Designing Flexible Hardware
December 3, 2009
10:00 - 11:00 CET
Learn more |
Wouldn’t it be great if you could
combine the flexibility of an FPGA with the efficiency of an ASIC?
If you could just take your RTL design and make it field programmable
while using the same implementation and verification technology?
Register for this FREE workshop today!
Designing Flexible Hardware
December 1, 2009, 9:00 – 15:00
CoWare‘s Munich Office
Herzog-Heinrich-Strasse 11-13 • 80336, Munich, Germany
Phone: +49
(0) 89-20913818 • Fax: +49 (0) 89-20913810
This free hands-on workshop will introduce you to one of the
industry’s most powerful hardware design solutions. The entire
flow is automated while providing full control over the design,
accompanied by innovative debugging environments that support you
from architecture definition to hardware prototyping and implementation.
You will learn how to:
- Represent FSMs and data paths in an architectural description
- Perform functional verification with an innovative debug solution
- Generate RTL models that exactly meet your specification
- Generate fast system-level models for platform-level validation
- Add flexibility by making the FSMs post-silicon-programmable
- Create, change and download post-silicon hardware configurations
in an innovative programming environment
Who should attend:
- Hardware architects and RTL designers
- Engineering management
Agenda:
- 9:00 - 9:30am Registration/Coffee
- 9:30 - 10:45am Design and Modeling of Custom Hardware
- 10:45 - 11:00am Break
- 11:00 - 12:00am Introduction to the “Design Kit“
- 12:00 - 1:00pm Lunch Break
- 1:00 - 3:00pm Optional: Lab/Workshop
- Modeling and Debugging
- RTL Code Generation
- System-Level Models
- Creation of Hardware Programs
Participation in the lab is optional. Attendees are expected to
bring their own laptop with a minimum free disk space of 1GB and
minimum RAM of 2GB.
If you are unable to attend the hands-on workshop on December
1st, please register to attend:
One-hour Webinar: Designing Flexible Hardware
December 3, 2009
10:00 - 11:00 Central European Time (CET)
During this webinar you will learn how to:
- Represent FSMs and data
paths in an architectural description
- Perform functional verification with an innovative debug solution
- Generate RTL models that exactly meet your specification
- Generate fast system-level models for platform-level validation
- Add flexibility by making the FSMs post-silicon-programmable
- Create, change and download post-silicon hardware configurations
in an innovative programming environment
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