CoWare Platform Architect
SystemC Platform Capture and Architecture Analysis
for Platform-driven ESL Design

Highlights:

• Rapid Capture and Configuration of Hierarchical SoC Platforms
• Superior Architecture and Performance Analysis for SystemC
• Rapid Exploration of Complex Interconnect and Memory Architectures
• Advanced Simulation, Debug, and Analysis for Software Development
• Automated Integration of RTL Blocks into the TLM System
• Automated Creation of Highly Reusable, User-defined SystemC Peripheral Components and Unit Tests
• Standards-based SystemC TLM Modeling Guidelines and Examples Using SCML
• Comprehensive SystemC IP Model Availability with the CoWare Model Library, CoWare Processor Designer, and Carbon Model Studio Support

Platform-driven ESL Design
The design of processor centric, software intensive product platforms poses a new set of requirements on the design tools and methodologies being used. The traditional EDA design flow from RTL to GDSII is no longer sufficient to capture the platform architecture, explore and evaluate alternatives, and eventually help optimize it. The platform architecture must be captured at a higher level of abstraction—processors, busses and peripherals need to be modeled in a manner that allows the execution of real software applications on the platform model so the performance of the architecture can be properly evaluated and explored.

For Platform-driven ESL Design, CoWare Platform Architect is the industry's most productive SystemC-based graphical environment for capturing the entire product platform and the dash board for initiating the platform analysis functions. Platform Architect's companion product, CoWare Model Designer, offers a stand-alone subset of these features to provide the industry's most productive SystemC-aware modeling, simulation, and debug environment for capturing complex IP blocks and verifying them at the transaction-level.

SystemC Platform Capture and Configuration
Platform Architect features the Platform Creator graphical user-interface for drag-and-drop assembly of SystemC transaction-level platforms based on the CoWare Model Library, user-defined libraries, and models generated by CoWare and 3 rd Party IP development tools. Because Platform Creator integrates simulation build, simulation run, and system-level analysis controls, platform developers can rapidly create and validate hierarchical, reconfigurable platforms from the within assembly environment. Developers can also easily export a fixed platform subsystem, which can then be imported by the SoC design teams for extension.

The on-chip interconnect architecture is critical to architectural optimization of the SoC. Using optional SystemC Transactional Bus Simulators, available in the CoWare Model Library for popular interconnect standards like AMBA, AXI, and OCP-IP, designers benefit from an off-the-shelf model library fully conforming with a given interconnect specification, fully instrumented for CoWare analysis, and fully configurable using Platform Creator for the desired interconnect topology. Models for customer bus and network-on-chip interconnect specifications can also be created. Platform Creator supports the creation of user-defined TLM protocols using standard SystemC channels, and allows for integration of user bus generators.

SystemC Platform-level Debug and Transaction Analysis
Debugging and transaction analysis of the virtual hardware platform is performed with Platform Architect's new SystemC Explorer tool. SystemC Explorer provides an easy-to-use graphical debugging environment, where the user can quickly browse the design hierarchy and attach monitors to any observable object in the SystemC platform. Examples of observable objects are TLM bus ports, member variables of SystemC models, and the signal ports. From the monitor view you can browse through the list of all monitors in the system, and with one click, send a group of monitors to the waveform viewer or message sequence chart for simulation. The resulting waveforms provide you with an overall view on the activity in the platform. From here you can quickly zoom in to observe the simulation results at the level of individual transactions.

The SystemC Explorer allows you to interrupt the simulation in many different ways. For example you can attach a process break on this thread, so the simulation will stop whenever this particular thread is activated. You can also set read, write, and access watch-points on specific registers. Event breaks on signal ports can be further configured to break only after the specified number of activations is reached. At any point in time during a SystemC Explorer session you can launch the DDD source-level debugger to set breakpoints in the SystemC source-code and control the simulation from inside the DDD. This way you can analyze the source code together with the overall activity in the system.

Superior Architectural and Performance Analysis for SystemC
Platform Architect's analysis tools provide textual and graphical views for the system designer, verification engineer, and software architect to analyze SoC architectures and performance, including critical items such as software execution and bus occupancy.

For architectural analysis, Platform Architect provides views to:

• Analyze cycle-accurate performance
• Study throughput and bottlenecks
• Look at bus switching and cache usage to reduce power
• Optimize bus & memory architecture

Or in the case of functional analysis, Platform Architect provides views to:

• Look at system response and task scheduling
• Analyze processor loading to drive partitioning
• Profile software for optimization
• Cross-correlate different views to extract powerful information

Analysis views can be configured at run-time using SystemC Explorer, enabling the user to decide on the data that is captured. The visualization environment allows the user to see the default graphical views dynamically during simulation or during post-processing to identify bottlenecks in the design. Views can be re-configured as required and data from multiple simulations can be grouped together for easy comparison of candidate architectures.   

Rapid Exploration of Complex Interconnect and Memory Architectures
Platform Architect's optional Architect View Framework (AVF) capability provides the additional ability to capture a platform in Platform Creator so it can be configured dynamically during run-time simulation. This enables very rapid architectural exploration through examination of different system parameters without the need to recompile; an otherwise a time consuming step. Parameters that can be modified without recompilation include: constructor parameters of modules, properties of modules, interconnect of modules, hierarchy, and bus IP parameters. Module and IP instances from the system library can be added or removed from the netlist. Other modifications will require recompilation. These features require use of the AVF Bus Library provided by CoWare, which delivers a generic point-to-point channel, simple shared bus, and network-on-chip cross-connect using protocol agnostic TL3 and OCP-IP TL2 levels of abstraction, and are supported by the optional Generic File Reader Bus Master (GFRBM) traffic generator and the Generic Memory Subsystem (GMEMSYS) IP models.

Advanced Simulation, Debug, and Analysis for Software Development
The CoWare Platform Architect Software Development option enables users of Platform Architect to access the same advanced simulation, debugging and analysis capabilities available to software developers through CoWare Virtual Platform. It allows platform modelers to validate the virtual platform, and the architect to execute software with the same capabilities as the software developers. The option includes:

• The execution of a simulation at high speed simulation using Instruction Accurate processor model and SCML based peripheral models
• The Virtual Platform Analyzer providing observability and controllability over the entire platform
• Software analysis enabling a better understanding of the system behavior.

Platform Architect's Virtual Platform Generation option allows for the distribution of CoWare Virtual Platforms across the enterprise, and to partners and customers by automating the packaging and licensing of the binary executable.  

Automated Integration for RTL Blocks into Transaction-level System
Availability of virtual hardware platforms for architecture design and software development can be accelerated through reuse of available RTL.Components generated by Carbon Model Studio plug directly into CoWare's standards-based SystemC environment and can be distributed to software users worldwide. Carbon Model Studio's graphical user interface enables the user to create a Carbon model, configure its software-visible registers, and link with Platform Architect's transaction-based interfaces for reuse across multiple abstraction levels and interconnects.

Platform Architect components generated by Carbon Model Studio are integrated through CoWare's SystemC Modeling Library (SCML). This gives system architects and software engineers debug visibility into the Carbon Model, as all registers and memories in any model can be queried, modified, or used as breakpoints. Carbon Models are completely hardware accurate and can generate waveforms for viewing in the CoWare environment. This enables software and hardware engineers to work together to debug complex system problems or any hardware problems uncovered by running software.

Platform Architect optionally provides HDL (Verilog or VHDL) block import, and automatically integrates these blocks into the transaction level system by generating the TLM to pin-accurate 'transactor' to connect the block onto the transaction-level bus.

• This makes it very easy to bring RTL blocks back into the system model, as each block is available from the hardware design team.
• At any stage of refinement, a mixed SystemC and HDL netlist can be created, complete with everything necessary to co-simulate with CoWare's range of supported HDL simulators and RTL verification flows from Cadence, Mentor, and Synopsys, including VHDL, Verilog, and e language interface support.
• In addition, Platform Architect also supports output of simulation tracing in FSDB format, for waveform viewing in the Novas Debussy Debug System.

A mixed-language simulation can then be performed as described for Platform Architect. This allows a powerful design for verification methodology enabling the SoC design team to:

• Use the TLM to RTL transactor generation to automate creation of consistent block interfaces that enable re-use of the system model, with embedded software, as the functional test bench
• "Divide and conquer" the burgeoning verification task by verifying each RTL "device under test" (DUT) in turn, enabled by automated block-level swapping of TLM and RTL models, and re-generating the mixed-level netlist with only the new DUT at RTL
• Integrate subsystem RTL generated using 3 rd party behavioral synthesis tools to validate candidate RTL implementations in the system with embedded software

SystemC Source-level Component Development and Unit Test
Platform Architect features the SystemC Component Wizard (SCWizard) graphical user-interface which greatly simplifies the creation of highly re-usable SystemC models of peripheral components. SCWizard guides the user through the definition of memories, memory-mapped registers and bit-fields, and SystemC transaction-level ports for the peripheral interface, as well as the SystemC processes, template and constructor parameters for the user-defined behavior. Based on this information the Component Wizard generates the html documentation, the SystemC source-code, and a file-driven unit test-bench. The results are observed in Platform Architect's SystemC Integrated Development Environment (SCIDE), where the user completes the source-code development, compiles the simulation, and debugs the behavior of the peripheral component.

SystemC Integrated Development Environment (SCIDE) based on Eclipse
Platform Architect features a powerful SystemC integrated development and debug environment (SCIDE) based on Eclipse--the industry's leading C++ development environment for embedded software. The integration adds SystemC graphical debugging and a managed build process to CoWare's optimized SystemC simulator and thread-aware debugging engine, improving debug productivity for SystemC model developers. Because Eclipse is open, users can also easily integrate Eclipse plug-ins into their CoWare environment. For more information about Eclipse and the availability of compatible 3 rd party plug-ins, see www.eclipse.org.

Graphical Tracing of SystemC Events, Threads, and IMCs
Platform Architect's graphical transaction tracing of SystemC events, threads, and Interface Method Calls (IMCs) improves debug visibility and provides a powerful way to visually debug TLM control flow through a system or between a block and its testbench. The view is presented in the style of a Message Sequence Chart. The graph easily shows dependencies between SystemC events and thread activations, and message sequences that trace IMCs - both without instrumentation. In addition, any transaction state that is captured using the transaction recording APIs provided by the SCV library can be added to the chart by the user.

SystemC TLM Modeling Guidelines and Examples Using SCML
The CoWare SystemC Modeling Library (SCML), along with modeling guidelines and source code examples, are available standard with Platform Architect to provide the infrastructure for user-defined, highly-reusable TLM peripheral models. SCML helps separate TLM communication, storage, timing, and behavior within the peripheral model, making code more modular and more efficient to develop and test. Models can be defined simply and annotated for timing when needed. Unlike proprietary modeling approaches, SCML is based on current IEEE SystemC, Open SystemC Initiative (OSCI), and Open Core Protocol International Partnership (OCP-IP) standards, helping protect the user's modeling investment.

In addition, modeling examples and transactors come standard with Platform Architect to make learning easier and provide a starting point for design. SystemC source-code for TLM platform examples and a generic IP library of platform building blocks are provided, including peripherals models, OCP interconnect, and transactors, channels, and bridges—all based on SCML. Note: CoWare's software license agreement provides users with access to the SystemC OCP models we distribute with full permission of OCP-IP. Users do not need to register separately at OCP-IP.org to use these models with CoWare tools.

IEEE 1666 SystemC, OSCI, and OCP-IP Standards Compatibility
Platform Architect's native SystemC simulation environment is compatible with IEEE 1666 SystemC Language Reference Manual (LRM), Open SystemC Initiative (OSCI) transaction-level modeling (TLM), and Open Core Protocol International Partnership (OCP-IP) TLM standards, providing support for all SystemC constructs for use by all members of a design team. Platform Architect also supports the OCSI SystemC Verification (SCV) 1.0 library extensions for transaction recording.

The SystemC language enables system-level design and IP exchange. SystemC delivers source code portability based on adherence to ISO C++ standards supported directly by Platform Architect. Any design created or developed using the IEEE 1666 SystemC compatible simulator can easily be run in Platform Architect at any level of abstraction.

Comprehensive SystemC IP Support with CoWare Model Library, CoWare Signal Processing Designer, and CoWare Processor Designer
The CoWare Model Library includes a range of processor models from leading vendors such as ARM and MIPS, transaction-level bus models and RTL bus generators for common bus specifications such as AMBA, AXI, and OCP-IP, Denali MMAV memory models, and peripheral models such as the ARM PrimeCells. Algorithmic models can be developed in CoWare's Signal Processing Designer then exported as SystemC models for import into Platform Architect. Similarly, models for custom processors, and other processors not supported in the model library, can be readily generated using CoWare Processor Designer and imported into Platform Architect.

Summary
Platform Architect is focused on making SystemC platform capture and architecture analysis for platform-driven ESL design a reality for SoC architects and design teams.

Platform Architect Benefits

• Deliver differentiated, superior products by finding the optimal hardware-software partitioning, interconnect and memory architecture
• Reduce product development risk while avoiding expensive over-engineering by confirming the architecture meets all performance, power and cost requirements prior to implementation
• Differentiate by automating on-chip interconnect implementation, allowing design resources to focus on value-added functions
• Easily create system-level models of platform subsystems for rapid evaluation, customization, and design-in.
• Bring better SoC-based convergent products to market, faster