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CoWare Signal Processing Designer
Implementing Algorithms for Platform-Driven ESL Design
Highlights
- Industry's fastest,
production proven signal processing simulator
- Fully supported on
Windows and Linux
- 4000+ models with
source code
- Unique standards
reference libraries
- Fully integrated
with MATLAB® and Catalytic MCS tools
- Fully integrated
into CoWare platform-driven ESL design solution
- RTL cosimulation support
for Cadence Incisive® and Mentor Modelsim®
- RTL code generation
for Synopsys DesignCompiler® and Cadence Encounter®
- Analog-Mixed Signal
(AMS) cosimulation with Cadence Incisive®
- One-click analysis
- Powerful polymodeling capability
- State-of-the-art GUI for maximum productivity
- Scalable XML database
- Automated model migration
from SPW designs
Overview
CoWare® Signal Processing Designer (SPD) accelerates the design
of complex, digital signal processing (DSP) systems. It is a C-based modeling
and simulation environment that facilitates structured modeling and model reuse
across design teams. Its efficient creation of complex DSP system models and
extremely fast simulation makes Signal Processing Designer the premier choice
for today's complex, multi-standard designs in the wireless and multimedia
markets. It is tightly integrated with the CoWare Platform Architect and CoWare
Processor Designer products.
Value
Designers of today's complex digital signal processing applications face a
number of product design challenges which require unique DSP design technology.
Optimization of the system cost and power consumption has the biggest impact
at the highest abstraction level, where algorithms are created and optimized
for the number and complexity of DSP operations needed. Differentiated algorithms
determine the user experience with the final product; whether it's the impact
of MIMO systems on Long-Term Evolution (LTE) wireless systems or the data rate
performance for HSPA or simply the cell phone speech performance. The specific
bit-accurate implementation requires not only design skills but specific DSP
design tool features to achieve the best quality in the minimum amount of design
time. For time to market, compliance to a particular standard is critical,
since a non-compliant device is rejected by the system operator. Also, a systematic
approach to verification and implementation into hardware and software is important
for predicting the time to working product.
The design time and cost are also influenced greatly through a systematic
approach to design reuse, which today has to start at the electronic system
level (ESL) and cannot be achieved with only some coding rules for C-based
modeling.
Solution
Design teams for large digital signal processing systems think
in block diagrams when they specify a system. Naturally, CoWare Signal Processing
Designer allows capture of the system exactly the same way--in a hierarchical block diagram
editor. System designers rely on reuse of fundamental algorithms, while being
adapted to specific system requirements through a set of parameters. A large
library of 4000+ blocks available for CoWare Signal Processing Designer allows
designers to quickly assemble the basic algorithms and set the parameters for
a specific application. The way a system designer will evaluate the system
performance and optimize it is typically through a large series of long simulations
of the system. This requires compilation of the underlying C-models in the
complex block diagram and then executing them in a specific order (also called
scheduling) to produce the desired outcome. Both the optimal scheduling sequence
and the optimization of individual signal processing operations, such as data-type
conversions, require sophisticated techniques which are built into the CoWare
Signal Processing Designer simulator. If design teams are working on a particular
standard, such as HSDPA, they can rely on pre-packaged libraries provided as
a reference for the standard. As opposed to individual designers exploring
smaller algorithms with MATLAB®, design teams using CoWare Signal Processing
Designer are working on total system design, where hundreds of complex individual
algorithms have to be integrated, most likely from different designers around
the world, today driven by the need for multi-standard, convergence products.
Library management and control features help keep the entire
design under control and tracking the design evolution as well as facilitating
structured reuse of designs. Typical life cycles for important reusable models
can span 5-10 years.
After initial optimization of the system using floating-point number representation,
the much more involved task of specifying the system at the fixed-point level
has to be performed. Customers will make use of the polymodeling feature, which
allows the designer to selectively switch between floating and fixed-point
representations, without changing the hierarchical block diagram. Reducing
the modeling effort to a single model, which can be parameterized across the
abstraction levels, is key to reducing the risk for the specification developed.
The final fixed-point model is then typically run through a large number of
regressions on a server farm in order to check the overall system performance
under all available scenarios. Selecting the servers involved and automatically
balancing the loads is enabled by configuring the interface to popular load
balancing utilities.
Many sophisticated users will model as well at the C-source code level, for
example to exactly mimic the production code in an embedded DSP. The interface
of a C-function into the CoWare Signal Processing Designer infrastructure is
very simple and makes integrating custom code, legacy models or using models
as embedded C-code easy. Designers benefit from the available 4000+ models,
which all come as source code and can be used as the starting point for modification.
The final verified model serves as bit-exact reference for verification of
the system. Any such model can be exported as a peripheral block into a transaction-level
SystemC platform into CoWare Platform Architect for usage as reference for
system verification. Also, if modeled accurately, any model can be exported
as a pin-level SystemC model, which either CoWare Platform Architect or leading
RTL simulation products with support for SystemC IEEE 1666. If a specific part
of the system is implemented as a custom processor, the processor model generated
by CoWare Processor Designer can be integrated into CoWare Signal Processing
Designer, thus facilitating the verification of the embedded code running on
the processor against the reference model.
Key Features
Getting Started
- Straightforward installation
- Integrated, self-paced
tutorial
Simulation
- Fast, compiled, one-click
simulation
- Optimizing static
scheduler covering wide range of models and variable data length during run-time
- Multi-rate simulation
and dynamic scheduling support without user intervention
- Support for server
farms running Sun® GridWare, extendable to other load balancing utilities
- Scripting with dynamically
changeable parameters
- Statistically equivalent,
parallelized bit-error-rate simulations
- User friendly error
message connected to cause of errors
Polymodeling
- Common functional
models operating with a wide range of different data types
- Packages the power
of C++ into a C-based environment with a simple structured modeling approach
- Parameters can be
complex functions defined with a C-compliant parameter expression language,
supporting the 'one-model' simulation approach
- Built-in source code
editor or user-defined external editor
Graphical Design Environment
- Microsoft® Windows
style graphical user interface with supported tabbed-design panes for compact
design representation and easy navigation
- High connectivity
between different design panes eases the tasks of assembling, parameterizing
and simulating a system
- Selecting an object
in one pane will cause the other panes to select the same object view
- Small number of clicks
to perform commonly-used design tasks
- Full flexibility
for symbol editing, colors and bitmaps to generate high quality documentation
of systems
- Tooltips for instances
in designs, models in the library browser and simulation parameters
Scalable Standard Data Model
- Standard XML views
for hierarchical models with clean separation of logical and graphical information
- Database scalable
for enhancements with more attributes, data type and parameters for future
design flow requirements
- Multiple, static
manipulations and analysis of the database can be performed through Tcl and
C++ programming interfaces; useful for corporate design methodology teams
MATLAB Integration
- MATLAB functions
can be integrated through automated calls to MATLAB engine
- Catalytic MCS optimized
C-models converted from MATLAB can be integrated through standard C-function
calls
- Simulation output
can be automatically redirected into MATLAB for analysis
Block Diagram Editor
- Easy graphic system
capture
- Unlimited undo/redo
operations
- Hierarchical block
diagram environment allows easy viewing of an entire system, including system
parameters and C source code
- Block terminals indicate
both signal direction and connectivity status
- Acrobat-style pan
mode with additional pan-overview window facilitating viewing of complex designs
- Simultaneous modification
of multiple selected objects properties
- Hierarchy refactor
for collapsing a group of models into one block
Library Browser
- Provides overview
of libraries, models and design hierarchies with short descriptions and symbol
views, logical views and structural views
- Powerful search function
across entire product and user data base
- Direct link from
library browser into the model documentation
Analysis
- Interactive analysis
supported by predefined analysis widgets (multitrace oscilloscopes, signal
generators, and spectrum analyzers, eye, scatter, x-y, parameters)
- Post-simulation analysis
with rich set of plot functions and post-processing and mathematical transformations
- Very powerful C-based
scripting of post-processing tasks, enabling subsequent one-click analysis
- Bit error rate (BER)
and block error rate (BLER) curves are automatically merged from a large number
of simulations conducted on multiple machines
- Analysis UI
handles manipulation of a variety of data types, including floating-point,
fixed-point and complex
- Signals and data
attributes can be collated and stored in a single file for analysis
- Automatic start of
MATLAB analysis from simulation results
Model Wizard
- Sophisticated infrastructure
to create templates for new blocks, which may be user-written polymodels
in C++, imported MATLAB functions, legacy C-functions, HDL or AMS
Workgroup/Data Management
- Control access and
modifications as well as revision history and track changes option with CVS
- Extendible to other
revision control infrastructures
Libraries & Options
Hardware Design System (HDS)
This option accelerates the hardware design, verification, and analysis of
complex, algorithm-intensive digital-signal processing (DSP) systems. The SPD
HDS flow provides graphical RTL design capabilities with parameterized design
capture that enable reuse. It also includes a large library of complex system
building blocks that contributes to substantial reductions in product development
time. Finally, it provides DSP design content captured and validated with SPD
at the data flow and implementation level to the verification engineers for
integration and test. In addition, AMS circuit and behavior models can be validated
within the SPD system context through cosimulation technologies. CoWare SPD supports
RTL simulators from Cadence and Mentor as well as RTL synthesis products from
Synopsys and Cadence.
Communications Library
The SPW Communications Library is a prebuilt collection of commonly used communication
functions, including basic capabilities like modulators, demodulators, adaptive
equalizers, error correction, filtering and channel models. These library functions
are available as both floating point and fixed point models. Also included
in this library are RF and Smart Antenna models. The RF library includes parameterizable
building blocks, such as amplifiers, mixers, and oscillators with phase noise,
which can be used in a cascaded stage analysis of the RF design. The Smart
Antenna Library assists in the development of MIMO (Multiple Input Multiple
Output) systems and design of transmit or receive diversity antenna systems.
End-to-end models and blocks for designing new Smart Antenna systems are provided.
DVB-S and DVB-H reference models are included.
WCDMA (3GPP) Library
The WCDMA Library conforms to Release 6 standards
to support the design of FDD and TDD modes of 3G Wideband CDMA (WCDMA) products.
Reference systems for 3GPP FDD mode are provided, such as uplink and downlink
transmission channel, fast cell search, downlink searcher and practical rake
receiver and uplink RACH model. HSDPA downlink/uplink model and TD-SCDMA uplink/downlink
models are part of the library. A rich set of libraries of fundamental CDMA
functions such as sequence generation, spreading and despreading, encoding/decoding,
and rate matching/interleaving operations as well as system test benches are
included. The library is currently being enhanced to support the specification
for Release 8 (LTE) standards.
WiMAX Library
CoWare® Signal Processing Designer WiMAX (Worldwide
Interoperability for Microwave Access) library is an environment for the development
of products based on IEEE 802.16-2004, IEEE 802.16e-2005 and IEEE 802.16-2004/Cor
1-2005 (Standards for Local and Metropolitan Area Networks: The Air Interface
for Fixed and Mobile Broadband Wireless Access Systems). The WiMAX library
contains both the basic blocks and the system models describing the IEEE802.16
WirelessMAN-OFDMA technology. This library can be used to develop systems and
ICs for building both fixed and mobile broadband wireless access systems that
cover a range of data rates between very high data rate wireless local area
networks and very high mobility cellular systems. It helps you design, implement,
and verify systems based on the WirelessMAN-OFDMA physical layer specification
of IEEE 802.16 standards for licensed and license-exempt frequencies below
11 GHz. It can significantly reduce your development time and can increase
your chance of first-time design success.
GSM/GPRS/EDGE Library
This library expedites the design of GSM/ GPRS/EDGE systems by facilitating
algorithmic exploration and shortening development and design verification
times. This library includes a rich set of libraries of fundamental GSM channels
such as Half Rate (TCH/HS), Full Rate (TCH/FS), Enhanced Full Rate (TCH/EFS)
and Full Rate/Half Rate Adaptive Multi-Rate (AMR). Additionally, vocoder models,
control channels such as BCCH, RACH, SACCH and FACCH, GSM Circuit Switched
Data (CSD) Channels such as Full Rate (TCH/F14.4, TCH/F9.6, TCH/F4.8, TCH/F2.4),
Half Rate (TCH/H4.8, TCH/H2.4), and the Enhanced Circuit Switch Traffic Channel
(E-TCH/ F28.8, E-TCH/F32.0, E-TCH/ F43.2) are included.
CDMA2000 (3GPP2) Library
The CDMA2000 Library provides a jump start to designers by covering the 1xRTT
modes as well as 1xEV/DV. End-to-end systems of forward and reverse links are
provided, including closed-loop power control. An end-to-end EV/DV model includes
the MAC layer to dynamically control modulation scheme, the number of Walsh
channels and sub-packet length.
WLAN/WPAN Library
The WLAN/WPAN Library is an environment for the development
of products based on IEEE802.11, IEEE802.11a, IEEE802.11b, IEEE802.11g, Hiperlan/2,
Bluetooth(TM) and
Ultra Wideband (UWB) wireless technology (both MBOA-UWB and DS-UWB). This environment
helps design, implementation, and verification of the physical layer baseband
of WLAN and WPAN systems.
Platforms
CoWare Signal Processing Designer runs on Linux and Windows. For specific
detailed platform information please contact CoWare sales. |
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