CoWare's application-specific subsystem development solution focuses on the design challenges that are developing due to the drastic changes in the subsystem architecture while migrating to next -generation standards.  

Replacement of a HW accelerator with a programmable accelerator: Convergence requires additional standards support at minimal additional cost. The high risk while transitioning to next-generation standards requires innovative architectures that meet performance and flexibility targets while minimizing risk specification mismatch. Risk management requires the ability to replace individual accelerators while keeping the overall subsystem architecture stable.

Firmware development for application-specific, multicore programmable solutions: Low-level software development productivity for multicore programmable solutions is the main barrier for the deployment of multicore systems to a broader market. Highly-skilled software developers are needed because FPGA or emulation boards with limited visibility and controllability are being used and because there is limited availability of basic software development tools.

Functional application verification: Increasing verification costs, the increasing number of modes in next-generation standards and higher time-to-market pressures increase the risk for re-spins due to specification mismatch and undetected errors in the system.  

Top-down flow for application-specific subsystem: Migration to next-generation standards requires modifications not only for the processing elements, but also for the data flow infrastructures. A very long, iterative approach with continuous, intermediate FPGA and ASIC tape-outs are used to show the feasibility of the architecture to meet performance and cost targets.

CoWare's Solution
CoWare provides a set of integrated design tools that support the individual design tasks described above and enable the iterative design process required to migrate to next-generation standards. With the tools' individual analysis and profiling capabilities together with configurable memory, interconnect and processor IP models, the user can quickly validate the performance of multiple, different architectures. With CoWare's extensive cycle-accurate processor and interconnect model library, the specification can be gradually refined while the performance is continuously validated and benchmarked. The fast, IP vendor certified models guarantee accurate prediction of performance together with early firmware development for future multicore systems.