CoWare's Platform Architecture Design Solution focuses on the challenges associated with the optimization and performance validation of the backbone interconnect and global memory subsystem of the SoC.  

Platform Architecture Design Challenges
Architects are looking to ESL methods to greatly improve the analysis and decision making process. They know RTL methods are too slow and lack the visibility needed to analyze design performance, configure complex on-chip interconnect, and optimize the global memory hierarchy. The results are over-design, cost increases, schedule delays, and re-spins.

Figure: Design Risks without ESL

Platform Architecture Design with CoWare
CoWare's Platform Architecture Design Solution provides our customers with production proven ESL technology and methodology to measurably improve their product performance and cost while reducing their design cycle time by 50% vs. traditional RTL methods.

Design Task: Interconnect and Memory Subsystem Performance Optimization and Validation Using Traffic Generation

Figure: Platform Architecture Design Using Traffic Generation

Measure, analyze, and optimize performance throughput before software is available using non-functional work load models to generate transaction traffic. CoWare Platform Architect enables users to:

• Assemble a cycle-accurate performance model
• Describe transaction traffic using standard input files
• Simulate with dynamic memory loads (via transaction traffic)
• Measure and analyzing performance (before SW is available)
• Optimize the configuration of complex interconnect
• Confirm accuracy with memory controller RTL

No IP modeling is required, enabling users to immediately assemble a cycle-accurate performance model of platform from CoWare IP Model Library components for traffic generation, interconnect, and the memory subsystem, and from Carbon Model Studio for the reuse of memory controller RTL. The resulting subsystem model is reusable in the full platform.

Design Task: Interconnect and Memory Subsystem Performance Optimization and Validation Using Cycle-accurate Processor Models and Software

Figure: Platform Architecture Design Using Cycle-accurate Processor Models and Software

Measure, analyze, and optimize performance throughput using a complete cycle-accurate platform model and software. CoWare Platform Architect enables users to:

• Assemble a cycle-accurate performance model of the platform capable of running the actual application software
• Debug the interfaces of newly integrated IP/Subsystem models
• Analyze contention for interconnect and memory subsystem resources to optimize the overall performance of a multi-processor system
• Optimize HW/SW partitioning of newly integrated IP/Subsystem models
• Achieve HW/SW product validation before RTL