CoWare's Platform Verification Solution focuses on the challenges associated with platform-level debugging and performance benchmarking of new IP/Subsystem RTL in the integrated system, by taking advantage of the cycle-accurate models developed for Platform Architecture Design.

Platform Verification Challenges
Hardware design teams are looking to ESL methods to greatly improve platform-level verification of multi-core designs. They know RTL methods are too slow and do not provide an efficient way to verify new IP/Subsystem RTL in the system context, causing reduced verification productivity, difficulty when benchmarking performance, and risks to product quality.

Figure: Design Risks without ESL

Platform Verification with CoWare
CoWare's Platform Verification Solution provides our customers with production proven ESL technology and methodology to measurably improve verification productivity and product quality, while reducing their design cycle time by 50% vs. traditional RTL methods.

Design Task: Platform-level Debug and Performance Benchmarking of Integrated IP/Subsystems

Figure: Platform Verification of New IP/Subsystem RTL

Debug and benchmark platform-level performance of new IP/Subsystem RTL using software and the cycle-accurate platform. CoWare Platform Architect enables users to:

• Reuse the cycle-accurate performance model developed for Platform Architecture Design as a Golden reference model for RTL
• Provide a realistic system context that significantly reduces test-bench creation effort at the RT level
• Ensure platform-level performance is not impacted by the performance of newly integrated IP/Subsystem RTL
• Achieve 10-100x improvement in product quality

The cycle-accurate platform model developed for Platform Architecture Design is fully reusable for Platform Verification. Development is accelerated through the availability of standard components from the CoWare IP Model Library, the use of CoWare's standards-based SCML modeling methodology for user-defined TLM peripheral IP, CoWare Processor Designer for the development of programmable hardware accelerator IP, and Carbon Model Studio for reuse of legacy RTL IP.