CoWare's Processor Design Solution focuses on the challenges associated with specific design tasks that take place both during and after the development of a programmable solution.

High-Speed Processor Modeling for Virtual Platforms: Limited speed as well as limited visibility and controllability of currently available Star IP processor models inside a virtual platform are preventing the successful deployment of virtual platforms for early SW development and early performance validation. To update the model to the latest simulation technology requires the implementation of the entire processor model which is a huge effort.

SW Development Tools Implementation: Low-level software development productivity of existing customized DSPs or custom processors limits the deployment of these customized solutions. The challenge is getting advanced software development tools, such as debuggers, simulation models, assembler, linker, macro-assembler, peephole optimizers, and C-Compilers into the hands of the software developers.

Processor Design for High-end Application Processors: Current DSPs are running into scalability limitations. They are no longer applicable for next-generation HD video and wireless base station systems. The challenge is the huge effort from concept to proof-of-concept for the next generation massive parallel programmable architecture. 150-200 person month effort can easily be deployed. Sometimes this effort is not even converging to a solution.

Processor Design for Programmable Accelerators: There are many factors that dictate the need for a programmable accelerator solution: multi-standard support, a large amount of modes in next-generation algorithm designs and the need for a 10X performance increase, just to name a few. Coupled with the large amount of varied skill sets required to provide a programmable solution that includes hardware, software and software development tools, developers today are faced with a huge challenge.  

Description of CoWare Solution
CoWare Processor Designer is a design automation tool for application-specific embedded processors and programmable accelerators. From one specification in LISA (Language for Instruction Set Architectures), the tool generates a high speed model, SW development tools such as debuggers, simulation models, assembler, linker, macro-assembler, peephole optimizers, and C-Compilers as well as RTL. Customers using CoWare Processor Designer for Design see 50% and more design effort reduction. Customer using it for modeling see a 10-100x speed improvement with the patented pending simulation technology compared to their existing models.