The design of product platforms poses a new set of requirements on the design tools and methodologies being used for SoCs. The traditional EDA design flow from RTL to GDSII is no longer sufficient to capture the platform architecture, explore and evaluate alternatives, and eventually help optimize it. The platform architecture must be captured at a higher level of abstraction--processors, busses and peripherals need to be modeled in a manner that allows the execution of real software applications on the platform model so the architecture can be properly evaluated and explored.

In SystemC this new level of abstraction above RTL is called transaction level modeling (TLM). Using CoWare's SystemC-based tools and transaction-level models designers can quickly create SoC platform models that deliver the range of simulation speed and accuracy required to perform and significantly expedite these critical but distinct SoC design tasks before the silicon or even the RTL implementation becomes available. This greatly improves the productivity to run and debug embedded software, investigate architectural alternatives, perform hardware/software integration, and validate the performance and efficiency of the resulting system.

The Transaction-level Modeling Investment

To get started, these ESL design tasks all require the availability of transaction-level models of the SoC platform. This significant investment in modeling can be mitigated by IP and ESL tool developers providing models for common-off-the-shelf IP such as processors, buses, and standard peripheral components. CoWare provides these today, for example, with the CoWare SystemC IP Model Library.

The majority of the platform specific IP blocks, however, need to be modeled by the ESL user. A standards-based methodology for the efficient creation of reusable transaction-level peripheral models is therefore one of the most important prerequisites for the successful adoption of ESL design.

Modeling TLM Peripherals Using SCML

CoWare provides the SystemC Modeling Library (SCML) API library, peripheral modeling guidelines, and generic examples with our tool environment to assist users in the creation of highly reusable SystemC transaction level peripheral models. This includes CoWare Platform Architect, Model Designer, and Virtual Platform Designer.

SCML peripherals follow a simple TLM pattern that separates peripheral behavior, storage, communication and timing in a way that makes model development more efficient—1/10th the effort of synthesizable RTL—and enables re-use of user-defined peripheral models across multiple design tasks and platforms. This approach helps improve the ROI of the user's ESL design methodology, extend the use of a model for additional ESL design tasks beyond the purpose of the initial model, and proliferate ESL design to other groups as they take advantage of existing models for their needs.

SCML is a fully open TLM methodology for SystemC peripherals based on existing industry standards from IEEE, OSCI, and OCP-IP. In addition, SCML will continue to support these standards as they evolve. CoWare is actively participating in these organizations—working together with our customers and partners—to influence the direction of SystemC TLM standards so they meet the interoperability requirements of models serving multiple ESL design tasks.

• To learn more, download the "TLM Peripheral Modeling for Platform-Driven ESL Design: Using the SystemC Modeling Library" white paper in English or Japanese

SCML Source Code Library Download

Meanwhile, in parallel to the standardization process, CoWare has developed a source code implementation of the SCML API library which is available today. The purpose is to protect user investment in user-defined SCML peripheral models by enabling their use in other IEEE 1666 compatible SystemC simulation environments. For more information on this kit, visit the download page below.

• SCML Source Code Library Kit download